EE 330 Final Project

Four-way Traffic Light Controller

 

This project is to use Verilog code to simulate a four-way traffic light system with two modes: automatic operation and manual operation (allow pedestrians to press the button). This is a group lab with two members. The intended purpose of the final project is to show logic analysis, Verilog and Hardware Description Languages (HDL) usage for the design.

 

My responsibility is to compile and test the Verilog code. I have drew all scenarios as well as the corresponding truth table. I wrote both simulation and test bench codes. At last, I obtained a simulation output to verify the accuracy of my code.

 

When my partner tried to do Verilog synthesis with RTL compiler, because of code format complexity, the compiler failed to yield a reasonable output. Therefore, I revised Verilog codes many times in order to get a desired schematics after synthesis. However, there still existed some parts were not compatible with the compiler at last, we have minimized the errors as possible as we can do. The code optimization and clarification will be my focus in my future design.